Name: Ask the Experts: Exploring the Impact of AI 2.0 on the Memory Landscape
Start: 2024-10-11T01:51:00Z
End: 2024-10-11T01:51:13.000Z
Location: BrightTALK
Rating: 0

Rambus makes industry-leading chips and IP that advance data center connectivity and solve the bottleneck between memory and processing. 

The ongoing shift to the cloud, along with the widespread advancement of AI across data center, 5G, automotive and IoT, has led to an exponential growth in data usage and tremendous demands on data infrastructure. Creating fast and safe connections, both in and across systems, remains one of the most mission-critical design challenges limiting performance in advanced hardware.

Rambus is ideally positioned to address this challenge as an industry pioneer with over 30 years of advanced semiconductor interconnect experience moving and protecting data. We are a leader in high-performance memory subsystems, providing chips, IP and innovations that maximize the performance and security in data-intensive systems.

Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data transfer speed and trust. Rambus products and innovations deliver the increased bandwidth, capacity and security required to usher in a new era of data center architectures and drive ever-greater end-user experiences.

We are excited to have guest speaker, Sharad Chole, Co-founder and Chief Scientist at Expedera, join us for this episode of Ask the Experts. Here, explores the evolution of AI as it is deployed as inference workloads at the edge. 

Expedera, a neural network IP provider, focuses on neural processing units (NPUs) for edge devices, emphasizing low-power operation, optimizing bandwidth, and cost efficiency. 

To learn more, visit: https://www.expedera.com/

Ask the Experts: AI at the Edge

In this episode of Ask the Experts, we sat down with Rambus memory expert John Eble to learn what’s new with DDR5 server memory modules (RDIMMs). Major topics discussed include:

The chips in DDR5 memory’s new RDIMM architecture
- The importance of memory module PMICs
-  New Rambus DDR5 server PMIC products
- Timing and enablement of DDR5 7200 server platforms

Ask the Experts: DDR5 Memory Interface Chips

In this episode of Ask the Experts, we discuss AI security with Scott Best, senior director of security products at Rambus.

Topics discussed include: 
- The challenges associated with securing AI
-  How hardware-level security is key for data privacy and data authenticity
- The security impact of quantum computing
- Rambus security IP solutions for AI silicon

Ask the Experts: Securing AI

In this episode of Ask the Experts, we discuss HBM3E memory with Nidish Kamath, Director of Product Management for Memory Interface IP at Rambus, and Frank Ferro, Group Director of Memory and Storage IP at Cadence.

Topics discussed include:
• The role HBM plays in today’s computing landscape
• Reasons why we’ve seen such a rapid evolution of the HBM specification in recent years
• Characteristics of HBM, and HBM3E specifically, that make it particularly suitable for AI training
• Challenges on the physical layer and memory controller sides to meet the higher performance targets of HBM3E
• How Cadence and Rambus work together to instantiate for the customer a complete HBM3E memory subsystem
• Where people can learn more about the Cadence and Rambus IP solutions for HBM3E

Ask the Experts: HBM3E Memory Interface IP

In this episode of Ask the Experts, we discuss the latest PCI Express (PCIe) developments with Lou Ternullo, Senior Director of Product Management at Rambus.

Topics discussed include:
• The applications driving the rapid advancement of PCIe
• What’s new in the PCIe 7.0 specification
• How PCIe 7.0 provides data protection
• Rambus PCIe 7.0 IP solutions
• Why choose Rambus for PCIe 7.0 digital IP

Ask the Experts: PCI Express 7.0 Interface IP

In this episode of Ask the Experts, we discuss DDR5 for client systems with John Eble, VP of Product Marketing, Memory Interface Chips at Rambus. 

Topics discussed include:
• The need for advanced chipsets for DDR5 client DIMMs
• The role of the DDR5 Client Clock Driver (CKD) and its use cases 
• The AI applications driving the need for greater memory performance in client systems

Ask the Experts: DDR5 Client Chipset

In this episode of Rambus “Ask the Experts,” we discuss HBM4 with Nidish Kamath, director of product management for memory interface IP at Rambus.  

Topics discussed include:  
- How AI is influencing the development of the HBM specification  
- What we know so far about HBM4
- The implementation challenges associated with HBM4
- The Rambus HBM4 Controller IP offering
- Why customers should choose Rambus for their HBM designs

Ask the Experts: HBM4 Controller IP

Join us as Ajay Kapoor discusses how Inline Memory Encryption can protect data moving between processors and attached memory. In this presentation, he’ll discuss: 
- Introduction to Inline Memory Encryption and its benefits 
- Techniques for integrating memory encryption into hardware designs
- Examples demonstrating effective use of inline memory encryption

Inline Memory Encryption Enabling Data in Use Protection for Confidential Computing

Join us as Maxim Demchenko provides a perspective on the security protocols used to protect data moving across global networks. In this presentation, he’ll discuss: 
- Overview of MACsec and its role in securing data link layers  
- Design and implementation of MACsec in hardware systems  
- Real-world applications and deployment scenarios across different markets

Network Security with MACsec and IPsec

Join us as Stuart Kincaid discusses how certified silicon IP can streamline the process of certification for chips and electronic systems. In this presentation, he’ll cover:  
- The role of certified silicon IP in enhancing hardware security  
- Standards for achieving silicon IP certification across different markets  
- Benefits of leveraging certified silicon IP solutions

Certified Silicon IP

With the arrival of quantum computers on the horizon, Bart Stevens provides perspectives of the consequences for digital security. In this presentation, he’ll discuss: 
- Overview of the quantum computing security threat  
- New quantum safe cryptographic algorithms   
- Preparing for a quantum future: strategies and considerations for a quantum safe SoC design

Protecting Devices and Data with Quantum Safe Cryptography

Join us as Parvez Shaik discusses the foundation of digital security, the Root of Trust. In this presentation, he’ll cover:  
- Overview of the importance of Root of Trust  
- Design principles for establishing a Root of Trust in hardware  
- Practical implementation strategies and best practices  
- Selecting the right Root of Trust IP for your project

Introduction to Root of Trust

In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has included an optional IDE (Integrity and Data Encryption). While IDE is optional today, given ever-increasing security threats, it won’t be forever so understanding IDE will become essential.
 
In this webinar, Rambus and Siemens will discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.

CXL and IDE: Important Considerations of Protecting High Speed Interconnects

The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Malini Narayanamoorthi and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. A demonstration of the silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller will be shown.

Selection and Implementation of a PCIe 5.0 Subsystem

As the need for data has exploded driven by applications like AI/ML and automotive, the semiconductor industry, led by PCI-SIG, is preparing for the final release of the PCIe 6.0 specification and all the changes it entails.

In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

What you will learn:

- what is PCIE 6.0
- how does it differ from past generations
- design considerations when planning with PCIe 6
- verification implications of a PCIe 6 design

Preparing for PCIe 6.0

Over the course of two decades, PCI Express® (PCIe®) has become the de-facto I/O interconnect in electronic systems, by providing the level of performance and reliability expected by cloud, enterprise, consumer, industrial, and automotive applications.
However the explosion of data in recent years has accelerated the need for higher performance interconnects, prompting PCI SIG® to quickly transition to PCIe 6.0 with the imminent release of the PCIe 6.0 specification.
In this webinar, we present the main characteristics of the PCIe 6.0 protocol in contrast to earlier revisions, and explain the rationale behind the main architecture changes. We then take a look at PCIe 6.0 from the perspective of silicon IP enablement, by introducing the main design features required to take full advantage of the new level of performance offered by PCIe 6.0.

Get ready for PCIe® 6.0, the next generation of I/O interconnect

As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architects to look for ways to differentiate and future-proof their designs.

In this presentation we look at current storage architectures and propose an innovative way to design next-generation storage SoCs centered around the use of embedded PCIe switching.

We then introduce PLDA’s PCIe switch IP along with some real-world use cases, and explore the various IP features and capabilities that enable differentiation and future-proofing of SoCs in storage applications and beyond.

Building Smart Scalable Storage SoCs with Embedded PCIe Switching (Chinese)

AI is a rapidly evolving space. With the meteoric rise of generative AI applications in the past year, we are now firmly in the era of AI 2.0. This is characterized by large language models that place AI into the hands of millions of consumers and enterprises offering limitless possibilities for creativity and innovation. We recently interviewed Dr. Steven Woo, fellow and distinguished inventor at Rambus Labs, to find out more about AI 2.0 and the key technologies that will shape it going forward.

Ask the Experts: Exploring the Impact of AI 2.0 on the Memory Landscape

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Ask the Experts: Exploring the Impact of AI 2.0 on the Memory Landscape

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