Name: Compute Express Link™ 2.0 Specification: Memory Pooling
Start: 2021-03-23T16:00:00Z
End: 2021-03-23T16:01:00.000Z
Location: BrightTALK
Rating: 4.6

Compute Express Link® (CXL®) is a new breakthrough high-speed CPU interconnect that enables a high-speed, efficient performance between the CPU and platform enhancements and workload accelerators.

 

Industry leaders Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements.

CXL® (Compute Express Link®) enables the addition of a new tier of memory to the memory hierarchy using type-3 devices. There are many first-generation CXL memory expansion devices in the market that will allow this capability. However, due to additional controller and board costs and associated power consumption, much of the value proposition of memory tiering is diluted. 

This webinar will outline a framework to enable CXL devices to be deployed at scale and allow the expansion of platform memory capacity incrementally and cost-effectively. The webinar will also explore how this framework will be a fundamental enabler for more ambitious CXL-enabled memory architectures in the future.

Making Memories at HyperScale with CXL®

CXL is an open coherent interconnect standard that enables heterogeneous computing, increases memory capacity and bandwidth, and optimizes performance for current workloads and emerging applications. CXL Consortium members are offering products based on the CXL 1.1 and 2.0 specifications and developing products based on the CXL 3.x specification. 

Join CXL Consortium member companies Astera Labs, Samtec, and UniFabriX as they highlight their ongoing work to create CXL solutions that addresses emerging use cases and applications. The webinar will explore CXL feature capabilities, implementations, and future capabilities of CXL devices.

Exploring CXL® Use Cases and Implementations

The CXL 3.1 Specification introduces enhancements to fabric capability and manager API definition for PBR switch, inter-host communication using Global Integrated Memory (GIM), Trusted-Execution-Environment Security Protocol (TSP), and memory expander improvements. These enhancements will enable composable and disaggregated systems to keep up with the demand for high-performance computational workloads.

This webinar will introduce the CXL 3.1 specification and explore the new features including: 
• CXL Fabric improvements and extensions 
• Trusted-Execution-Environment Security Protocol (TSP) 
• Memory expander improvements

Introducing the CXL 3.1 Specification

CXL’s advanced memory expansion and fabric management capabilities can be used to increase system scalability and flexibility across multiple compute domains, enabling resource sharing for higher performance, reduced software stack complexity, and lower overall datacenter memory cost. The fabric enhancements and memory expansion features included in CXL 3.0 deliver new levels of composability required by the large models used in HPC and AI in the modern datacenter. 

In this webinar, expert representatives from CXL Consortium member companies who are implementing the specification will explore the CXL 3.0 features, new use case enablement, and ROI examples when implementing CXL attached memory.

Increasing Memory Utilization and Reducing Total Memory Cost Using CXL

CXL Consortium member companies are developing a wide range of products and solutions including CXL memory solutions, IP, compliance testing, fabric implementations, switches, and software solutions. Compliance and interoperability between these products are essential to creating a technology standard that will be successfully deployed in commercially available systems across multiple vendors.

This webinar will highlight the ongoing work of the CXL Consortium Compliance Working Group to develop and expand the CXL Compliance Program and will include an overview of the recent CXL 1.1 and pre-FYI 2.0 test event, the Consortium’s Integrators List, and discuss future Compliance Test Events. Attendees will learn about upcoming developments in CXL testing methodology and CXL 2.0 compliance testing.

CXL Consortium Compliance Program Overview: Integrators List & Feature Testing

Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion, and accelerators. CXL enables a high-speed, efficient interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs, and other purpose-built accelerator solutions. At Supercomputing 2022 (SC’22), CXL Consortium members showcased CXL technology demonstrations on memory solutions, IP, compliance testing, fabric implementations, switches, and software solutions. 

The webinar will provide an update from the CXL Consortium, highlight the industry ecosystem and technology demos shared at SC’22, and discuss evolving CXL use cases. A Q&A session featuring member company representatives who showcased a CXL demo at SC’22 will close out the webinar.

A look into the CXL device ecosystem and the evolution of CXL use cases

In August 2022, CXL Consortium released the CXL 3.0 specification. CXL 3.0 expands on previous technology generations to increase scalability and optimize system level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. It also doubles the data rate to 64 GT/s with no added latency over CXL 2.0, while maintaining backward compatibility with previous specifications. 

This webinar will introduce the CXL 3.0 specification and explore the new features including: 
• Fabric capabilities and management
• Dynamically composable systems
• Improved memory sharing and pooling
• Enhanced coherency
• Peer-to-peer communication 
• Doubled data rate with no added latency

CXL 3.0: Enabling composable systems with expanded fabric capabilities

Compute Express Link™ (CXL™) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 1.1 specification introduced and defined the CXL I/O protocol, memory protocol, and coherency interface. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory.

This webinar will share a high-level overview of CXL 1.1, and the enhancements made in CXL 2.0 focusing on switching, memory pooling, Single Logical Devices (SLD) vs. Multiple Logical Devices (MLD), and fabric management. The presentation will also explore managed hot-plug, memory QoS telemetry, speculative reads, and security enhancements.

CXL 1.1 vs. CXL 2.0 – What’s the difference?

Compute Express Link™ (CXL™) is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers and smart I/O devices. The CXL 2.0 specification introduces a standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.

This webinar will introduce the CXL™ Fabric Manager (FM), explore Multi-Logical Device (MLD) management, and detail the Component Command Interface (CCI) transport protocols, background operations and categories of requests. The presentation will also share an architectural overview of the CXL 2.0 management framework and how it addresses the requirements of enterprise and datacenter deployments.

Introduction to the Compute Express Link™ (CXL™) Fabric Manager

In November 2020, the CXL Consortium released the CXL 2.0 specification which introduces support for switching, memory pooling, and support for persistent memory – all while preserving industry investments by supporting full backward compatibility. Based on member feedback, CXL 2.0 ECNs made significant improvements to the specifications in the areas of device management, RAS, Security, memory interleaving and others.

This webinar will review the key CXL 2.0 specification ECNs and the new usages they enable.

An Overview of the Compute Express Link™ (CXL™) 2.0 ECN

Security is a key cornerstone for any technology to be successful and CXL is making great strides in security by working collaboratively with other industry-standard bodies such as PCI-SIG and DMTF to ensure a seamless user experience with the best security mechanisms. CXL 2.0 enhances the security mechanism from CXL 1.1 and 1.0 by adding link-level Integrity and Data Encryption (CXL IDE) to provide confidentiality, integrity and replay protection for data transiting the CXL link.

This webinar will explore CXL IDE usage models and how security is managed across CXL.io, CXL.mem, CXL.cache and CXL Switches. The webinar will also explore a Device’s responsibility to maintain security.

Compute Express Link™ (CXL™) Link-level Integrity and Data Encryption (CXL IDE)

Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification introduces support for switching, memory pooling, and persistent memory – all while preserving industry investments by supporting full backward compatibility.
An increasing number of applications — ranging from databases to AI workloads — are being enhanced to take advantage of persistent memory. This webinar will explore how the CXL specification has evolved to support persistent memory devices in a way that preserves the established software model. This webinar will cover enhancements to the CXL protocol, error handling, and standardized configuration interface, enabling innovative designs that are based on a variety of non-volatile media and form factors.

Compute Express Link™ (CXL™): Supporting Persistent Memory

The CXL Consortium is proud to announce the second-generation Compute Express Link™ (CXL™). CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. 

This webinar will explore the new features in the CXL 2.0 specification including support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory – all while preserving industry investments by supporting full backward compatibility with CXL 1.1 and 1.0.

Introducing the Compute Express Link™ 2.0 Specification

Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion and accelerators. CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CXL.io, based on PCIe®), caching (CXL.cache) and memory (CXL.memory) semantics. CXL.mem allows a host processor to access memory attached to a CXL device. CXL.mem transactions are simple memory load and store transactions that run downstream from the host processor which takes care of all the associated coherency flows. 

This webinar will explore how the CXL.mem protocol can deliver power-efficient performance with emerging applications such as AI, HPC, DL and comms with a coherent interface and low latency. This webinar will also explore type-3 devices and use cases for memory bandwidth expansion, memory capacity expansion and storage class memory.

Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions

CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. In CXL, the CPU host is primarily responsible for coherency management abstracting peer device caches and CPU caches. The resulting simplified coherence model reduces the device cost, complexity and overhead traditionally associated with coherency across an I/O link. 

Please join Siamak Tavallaei, CXL Consortium Technical Task Force Co-Chair and Principal Architect, Microsoft Azure, Rob Blankenship, Processor Architect and Principal Engineer, Intel, and Kurt Lender, CXL Consortium Marketing Working Group Co-Chair and Senior Ecosystem Enabling Manager, Data Center Group, Intel, for a deep dive into how CXL technology maintains memory coherency between the CPU memory space and memory on attached devices. The webinar will also detail several representative CXL use cases – Caching Devices/Accelerators, Accelerators with Memory, and Memory Buffers. 

Following the webinar, we will host an audience Q&A, so be sure to bring your questions.

Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases

A highly informative webinar about the CXL Consortium™ and its groundbreaking technology.

Join Glenn Ward, CXL Consortium’s MWG Co-Chair and Chief of Staff, Cloud Server Infrastructure for Microsoft; Debendra Das Sharma, Intel Fellow at Intel Corporation; and Kurtis Bowman, CXL Consortium Board Member and Director, Server Architecture and Technologies at Dell EMC during this thought-provoking webinar about the organization and its innovative technology. Topics covered include the industry landscape, features and benefits, use cases and more! All audience members are encouraged to bring questions for the Q&A portion of the webinar. Learn about how the organization operates and how to get involved.

Introduction to Compute Express Link™ (CXL)

Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. In November 2020, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and support for persistent memory – all while preserving industry investments by supporting full backward compatibility.

In this webinar, Mahesh Wagh (Intel) and Rick Sodke (Microchip), will explore how CXL 2.0 supports memory pooling for multiple logical devices (MLD) as well as a single logical device with the help of a CXL switch. This presentation will also introduce the standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.

Compute Express Link™ 2.0 Specification: Memory Pooling

accelerators

Cache-coherent

Caching

Compute Express Link

interconnect

memory

memory pooling

Storage

Storage Industry

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Compute Express Link™ 2.0 Specification: Memory Pooling

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