Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases

CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. In CXL, the CPU host is primarily responsible for coherency management abstracting peer device caches and CPU caches. The resulting simplified coherence model reduces the device cost, complexity and overhead traditionally associated with coherency across an I/O link. Please join Siamak Tavallaei, CXL Consortium Technical Task Force Co-Chair and Principal Architect, Microsoft Azure, Rob Blankenship, Processor Architect and Principal Engineer, Intel, and Kurt Lender, CXL Consortium Marketing Working Group Co-Chair and Senior Ecosystem Enabling Manager, Data Center Group, Intel, for a deep dive into how CXL technology maintains memory coherency between the CPU memory space and memory on attached devices. The webinar will also detail several representative CXL use cases – Caching Devices/Accelerators, Accelerators with Memory, and Memory Buffers. Following the webinar, we will host an audience Q&A, so be sure to bring your questions.