Ensuring PCI Express® Signal Integrity for AI/ML Architectures

In Artificial Intelligence (AI) and Machine Learning (ML) applications, where data demands and processing speeds are continually increasing, ensuring robust signal integrity in PCI Express® (PCIe®) channels is critical. This PCI-SIG® webinar will provide a comprehensive look at the signal integrity challenges inherent to high-bandwidth AI applications, including jitter and crosstalk, and the new implications introduced by the evolution from PCIe 5.0 to PCIe 6.0 and PCIe 7.0 specifications and the transition to PAM4 signaling. Technical experts from Astera Labs, Samtec and Synopsys will explore the pivotal role PCIe technology plays in enabling high-performance, reliable connections in AI/ML infrastructures. Beginning with an overview of the common signal integrity challenges, the discussion will cover Nyquist frequency changes from the PCIe 5.0 specification through the PCIe 7.0 specification (targeted for release in 2025), and examine how the transition to PAM4 signaling helps to achieve acceptable Bit Error Rate (BER) thresholds. The presenters will review the PCI-SIG defined channel for CEM AICs and extenders for PCIe 5.0 and 6.0 specifications. They will also cover the impacts of crosstalk from AI architectures that demand numerous PCIe PAM4 lanes to switch simultaneously on die and the package, using a case study to highlight real-world challenges. Attendees will gain insight into the PICMG COM-HPC defined channels for PCIe 5.0 and 6.0 specifications and understand the channel loss budgets – both for internal and external cabling – and the role of retimers to extend reach while maintaining signal integrity. Join the educational webinar to learn the latest advancements and best practices for maintaining error-free, high-speed connectivity across evolving PCIe channels.